NXP Semiconductors /LPC11E6x /PINT /PMCTRL

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Interpret as PMCTRL

31282724232019161512118743000000000000000000000000000000000000000000 (PIN_INTERRUPT_INTER)SEL_PMATCH0 (DISABLED_RXEV_OUTPU)ENA_RXEV0RESERVED0PMAT

ENA_RXEV=DISABLED_RXEV_OUTPU, SEL_PMATCH=PIN_INTERRUPT_INTER

Description

Pattern match interrupt control register

Fields

SEL_PMATCH

Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function.

0 (PIN_INTERRUPT_INTER): Pin interrupt. Interrupts are driven in response to the standard pin interrupt function

1 (PATTERN_MATCH_INTER): Pattern match. Interrupts are driven in response to pattern matches.

ENA_RXEV

Enables the RXEV output to the ARM cpu and/or to a GPIO output when the specified boolean expression evaluates to true.

0 (DISABLED_RXEV_OUTPU): Disabled. RXEV output to the cpu is disabled.

1 (ENABLED_RXEV_OUTPUT): Enabled. RXEV output to the cpu is enabled.

RESERVED

Reserved. Do not write 1s to unused bits.

PMAT

This field displays the current state of pattern matches. A 1 in any bit of this field indicates that the corresponding product term is matched by the current state of the appropriate inputs.

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